SynthRisk

SynthRisk is a tool built by one developer (Sangsoo Park) that uses GPT-5.6 to triage RTL lint warnings based on synthesis risk rather than rule severity. The description states it wraps an existing linter (Verible) with AI to prioritize issues that could lead to unintended hardware behavior, distinguishing between style nits and critical problems that become broken silicon. It is positioned as a complement to traditional linting, not a replacement, and claims to detect risks like inferred latches that standard linters miss.

The author reports building the entire tool in about a day using Codex (GPT-5.6 Terra), with prompts driving module generation. The tool sends lint output plus source code to GPT-5.6 for risk classification, returning JSON-formatted results with plain-language explanations and suggested fixes — but never rewriting RTL.

Key open question: Does this approach work reliably in practice? The description does not provide evidence of real-world usage, performance on large designs, or validation against actual hardware failures.

The description states that SynthRisk:

• Wraps an existing RTL linter (Verible) with GPT-5.6
• Classifies lint violations by synthesis risk — critical / warning / style
• Detects risks like inferred latches that the linter never flags
• Reports findings in a risk-sorted format, each with plain-language explanation and suggested fix
• Does not rewrite RTL code; only suggests fixes
• Runs via CLI, using OpenAI API to call GPT-5.6-terra

The tool is built entirely with Codex (GPT-5.6 Terra) in a spec-driven workflow, where modules were generated from detailed prompts and verified against real Verible output.

The author states that SynthRisk was inspired by frustration with current RTL lint tools:

• Linters report rule violations, not circuit consequences
• Warnings are treated equally regardless of impact
• Critical issues get lost in noise of style warnings
• In silicon, bugs cannot be patched after release — respins cost millions

The tool's positioning evolved from a "nice-to-have" to a core feature:

• Early realization that Verible doesn't flag inferred latch risks even with --ruleset=all
• This led to GPT-5.6 being used to detect risks directly from source, not just re-rank warnings
• The tool is positioned as complementing the linter, not replacing it

The author claims the approach works well:

• Correctly detects an inferred-latch risk that the linter stays silent on
• Triage is genuinely discriminating — different types of issues get different risk levels
• Zero false alarms on clean code
• Built end-to-end in about a day entirely with Codex

The description states:

• The tool is for digital circuit designers working on RTL (SystemVerilog)
• Specifically mentioned: "base die of HBM (High Bandwidth Memory)"
• The author identifies as a digital circuit designer
• The tool addresses the needs of those who write RTL and run lint tools daily
• The context is hardware design, not software development

No specific customer segments or personas are named beyond the general category of RTL designers working on physical circuits.

Not evidenced. The description does not contain any information about pricing, monetization strategy, or business model.

The description states:

• Built entirely with Codex (GPT-5.6 Terra)
• Spec-driven workflow: each module generated from detailed prompt
• Verified against real Verible output before committing
• Runtime triage engine calls GPT-5.6-terra via OpenAI API
• One request per file, with source and violations batched into structured JSON prompt
• CLI-based tool
• Handles Verible's nonzero exit code on violations
• Parses both single-column and range positions
• Strips stray markdown fences from JSON responses

The commit history is said to document each Codex-generated change.

Not evidenced. The description does not contain any information about:

• Revenue or customers
• Adoption metrics
• Usage statistics
• Product maturity beyond the hackathon submission
• Any form of traction or market validation

The description states that:

• RTL linting is a solved problem for detection but not for prioritization and consequence
• Traditional linters (like Verible) are better at finding rule violations than reasoning about consequences
• The tool fills the gap by using LLMs to reason about what violations mean for resulting circuits
• The architecture is "AI on top of lint", not "AI instead of lint"
• Future plans include supporting additional linters (Synopsys SpyGlass) behind same triage layer

No competitors or competitive landscape are named.

Inferences based on the description:

• Reliance on GPT-5.6 for critical hardware decisions may be risky due to LLM hallucination
• The tool is positioned as complementing, not replacing, linters — suggesting it's not yet mature or trusted enough for full replacement
• No evidence of real-world validation or testing on large-scale designs
• The author states the tool was built in about a day with Codex — raises questions about robustness and long-term maintainability
• The approach assumes that GPT-5.6 can reliably detect synthesis risks from source code, which may not generalize well

1. What is the actual accuracy rate of GPT-5.6 in detecting real synthesis risks vs. false positives?
2. How does the tool handle edge cases or complex RTL patterns that might confuse the AI?
3. Has it been tested on large, real-world designs with hundreds of thousands of lines of code?
4. What is the performance overhead of running GPT-5.6 on every linted file?
5. Are there any known limitations or blind spots in how GPT-5.6 interprets RTL source?
6. How does the tool integrate into existing design flows and CI/CD pipelines?
7. What are the plans for supporting other EDA tools beyond Verible?
8. Is there any plan to make this commercially available, or is it purely a proof-of-concept?